1. Technical Field
This invention relates generally to oscillators, and more particularly to a current-controlled oscillator (ICO) with noise isolation feature.
2. Discussion of Background Art
Voltage controlled oscillators (VCOs) normally comprise a voltage-to-current converter circuit providing a current to control a current-controlled oscillator (ICO). ICOs, or VCOs as a whole, are susceptible to noise asserted from neighboring integrated circuits through the process substrate (or bulk) forming the transistors in ICOs. A Metal-Oxide Semiconductor (MOS) transistor includes a source, a drain, and a gate where the conductivity of the transistor is determined by a voltage V.sub.GS across the gate and the source. This voltage V.sub.GS determines the transistor's electrical performance because it determines the amount of current flowing through the transistor. Noise, or unwanted random electrical modulation of the substrate under the gate of a transistor, effects voltage V.sub.GS and causes the transistor to change its electrical behavior intended for its function.
Prior art solutions deal with ICO's noise problems based on the substrate resistivity because the substrate resistance permits noise to proliferate. Low resistivity substrates attenuate noise to a lesser extent than high resistivity substrates. One solution to deal with low resistivity substrates provides an unused area around the ICO circuitry, to create a barrier preventing noise from being injected into the ICO. Another solution provides either a p-channel or an n-channel ring serving as noise containment. This solution thus requires additional circuitry on the die comprising the ICO. Further, as current sub-micron technologies move towards low resistivity substrates, such solutions for high resistivity substrates become obsolete.
Most MOS processes include p-subtrates and n-wells. A solution dealing with noise in low resistivity substrates employs an n-channel isolation (n-ISO) technique, which provides a p-well inside an n-well, thus allows n-channels in a p-well inside an n-well. However, this n-well ISO technique requires an additional process step that takes an extra lithography step to put the p-well inside the n-well, which not only increases process cost and manufacturing time but also results in higher chances of low product yields.
Therefore, what is needed is ICO designs with noise immunity circuitry that overcomes prior art deficiencies.